For system-on-chip processors, progress has been made towards synthesis of application-specific-instruction-set processors (ASIP), including the generation of complete instruction sets for specific applications. Typically, the goal is the design of an instruction set for which a performance metric is optimized, e.g. minimization of run time, program memory requirements, or execution unit count. Application-specific instructions may be termed complex computer operations, including vector operations, fused operations, specialized operations and the like.
Recent attention has been given also to extending generic processors with units that are more broadly applicable, e.g. in a specified domain of applications. A typical goal of such processor extensions is optimization in the application domain without incurring the area and cost of top-of-the-line superscalar or multithreaded processors. An important motivation towards specialization of existing processors versus the design of complete ASIP's is to avoid the complexity of a complete processor and toolset development. Instead, an available and proven processor design and its extensible toolset can be leveraged, with design efforts focused on a special datagraph.
One method for generating an instruction-set extension from a description of an application is described in published U.S. Patent Application No. US 2003/0074654 by Goodwin et al., entitled “Automatic Instruction Set Architecture”. Described there is a basic fusion algorithm.